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4.4.1
Register Write Request
During a register write request, bits 12 through 8 contain a five-bit address, and bits 7 through 0 contain the data value to be
written. Writable registers are defined in Table 3 .
The response to a register write operation is shown in Table 30 . The response is transmitted on the next SPI message if and
only if all of the following conditions are met:
? No SPI Error is detected (Reference Section 4.5.1 )
? No MISO Error is detected (Reference Section 4.5.2 )
? The ENDINIT bit is cleared (Reference Section 3.1.6.2 )
– This applies to all registers with the exception of the DEVCTL register
? No Invalid Register Request is detected (Reference Section 4.5.3.2 )
If the above conditions are met, MMA68xx responds to the register write request as shown in Table 30 . Otherwise, MMA68xx
Responds as specified in Section 4.5 .
Register write operations do not occur internally until the transfer during which they are requested has been completed. In the
event that a SPI Error is detected during a register write transfer, the write operation is not completed.
4.4.2
Register Read Request
During a register read request, bits 12 through 8 contain the five-bit address for the register to be read. Bits 7 through 0 must
be logic ’0’. Readable registers are defined in Table 3 .
The response to a register read operation is shown in Table 30 . The response is transmitted on the next SPI message if and
only if all of the following conditions are met:
? No SPI Error is detected (Reference Section 4.5.1 )
? No MISO Error is detected (Reference Section 4.5.2 )
? No Invalid Register Request is detected (Reference Section 4.5.3.2 )
If the above conditions are met, MMA68xx responds to the register read request as shown in Table 30 . Otherwise, MMA68xx
responds as specified in Section 4.5 .
4.5
Exception Handling
The following sections describe the conditions for each detectable exception, and the MMA68xx response for each exception.
In the event that multiple exceptions exist, the exception response is determined by the priority listed in Table 33 .
Table 33. SPI Error Response Priority
Error Priority
1
2
3
4
5
6
7
8
9
Exception
SPI Error
SPI MISO Error
Invalid Request
DEVINIT Bit Set
DEVRES Error
CRC Error
Self-Test Error
Offset Monitor Over Range
ΣΔ Over Range
SPI Data
Error Response
Error Response
Error Response
Error Response
Error Response
Error Response
Error Response
No Effect
No Effect
Effect on Data
Arming Output
No Update
No Update
No Update
No Update
No Update
No Update
No Update
No Effect
No Effect
PCM Output
No Effect
No Effect
No Effect
Disabled
Disabled
No Effect
No Effect
No Effect
No Effect
MMA68xx
Sensors
48
Freescale Semiconductor, Inc.
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